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DATA SHEET
TDA6404; TDA6405; TDA6405A 5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Product specification Supersedes data of 1998 Jan 19 File under Integrated Circuits, IC02 1999 Jan 13
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
FEATURES * Single chip 5 V mixer/oscillator-PLL synthesizer for hyperband tuners * I2C-bus protocol * 3 PNP band switch buffers (25 mA) * 33 V tuning voltage output * In-lock detector * 5-level Analog-to-Digital Converter (ADC) * 15-bit programmable divider * Programmable reference divider ratio (512, 640 or 1024) * Programmable charge pump current * Balanced mixer with a common emitter input for VHF (single input) * Balanced mixer with a common base input for UHF (double input) * 4-pin common emitter oscillator for VHF * 4-pin common emitter oscillator for UHF * IF amplifier with a low output impedance to drive a SAW filter directly (2 k load) * Low power, low radiation, small size APPLICATIONS * Hyperband tuners for Europe using a 2-band mixer/oscillator in a switched concept. GENERAL DESCRIPTION The TDA6404, TDA6405 and TDA6405A are programmable 2-band mixer/oscillator-PLL synthesizers intended for VHF/UHF and hyperband tuners (see Fig.1). The devices include two double balanced mixers and two oscillators for the VHF and UHF band, an IF amplifier and a PLL synthesizer. With proper oscillator application and by using a switchable inductor to split the VHF band into two sub-bands (the full VHF/UHF and hyperband) the TV bands can be covered. Two pins are available between the mixer output and the IF amplifier input to enable IF filtering for improved signal handling. Three PNP ports are provided for band switching. Band selection is made according to the band switch bits VHFL, VHFH and UHF.
TDA6404; TDA6405; TDA6405A
The PLL synthesizer consists of a divide-by-eight prescaler, a 15-bit programmable divider, a 4 MHz crystal oscillator and its programmable reference divider and a phase comparator combined with a charge pump which drives the tuning amplifier, including 33 V output. Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 7.8125 kHz, 6.25 kHz or 3.90625 kHz. The devices are controlled according to the I2C-bus format. The in-lock detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (status byte) during a read operation. The ADC input is available for digital Automatic Frequency Control (AFC). The ADC code is read during a read operation on the I2C-bus (see Table 9). In test mode, pin ADC is used as a test output for fREF and 12fDIV. When the charge pump current switch mode is activated and the loop is phase-locked the charge pump current value is automatically switched to LOW. This is to improve carrier-to-noise ratio. The status of this feature can be read in the ACPS flag during a read operation on the I2C-bus (see Table 7). Five serial bytes (including address byte) are required for the I2C-bus format to address the devices, select the VCO frequency, program the three PNP ports, set the charge pump current and to set the reference divider ratio. The devices have four independent I2C-bus addresses which can be selected by applying a specific voltage on the AS input (see Table 4).
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
QUICK REFERENCE DATA SYMBOL VCC ICC fXTAL Io(PNP) Tstg Tamb f(i)RF GV F Vo PARAMETER supply voltage supply current crystal oscillator frequency PNP port output current IC storage temperature operating ambient temperature RF input frequency voltage gain noise figure output voltage causing 1% cross modulation in channel VHF band UHF band VHF band UHF band VHF band UHF band VHF band UHF band CONDITIONS operating all PNP ports are `OFF' RXTAL = 25 to 150
TDA6404; TDA6405; TDA6405A
MIN. 4.5 - 3.2 - -40 -20 45.25 - - - - - -
TYP. 5 78 4.0 - - - - 27 38 8 8.5 119 118
MAX. 5.5 - 4.48 25 +150 +85
UNIT V mA MHz mA C C
399.25 MHz 855.25 MHz - - - - - - dB dB dB dB dBV dBV
407.25 -
ORDERING INFORMATION TYPE NUMBER TDA6404TS; TDA6405TS; TDA6405ATS PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm VERSION SOT341-1
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
BLOCK DIAGRAM
TDA6404; TDA6405; TDA6405A
handbook, full pagewidth
IFFIL1
IFFIL2 6 (23)
VCC 17 (12) BSVHF (4) 25 (3) 26 VHF OSCILLATOR VHFOSCIB1 VHFOSCOC1 VHFOSCOC2 VHFOSCIB2
5 (24)
VHFIN
3 (26)
RF INPUT VHF
VHF MIXER
(2) 27 (1) 28
RFGND
4 (25)
BSVHF (11) 18 ELECTRONIC BAND SWITCH BSUHF BSUHF (5) 24 (6) 23 RF INPUT UHF UHF MIXER UHF OSCILLATOR (7) 22 (8) 21 (15) 14 (14) 15 UHFOSCIB2 UHFOSCOC2 UHFOSCOC1 UHFOSCIB1 CP VT DIGITAL PHASE COMPARATOR CHARGE PUMP TUNING AMPLIFIER IF AMPLIFIER IFOUT1 IFOUT2
BS
(10) 19
UHFIN1 UHFIN2
1 (28) 2 (27)
XTAL
16 (13)
XTAL OSCILLATOR 4 MHz
REFERENCE DIVIDER 512, 640, 1024
fREF
RSA
RSB
fDIV
T2, T1, T0 CHP IN-LOCK DETECTOR OS LOGIC
PRESCALER DIVIDE BY 8
15-BIT PROGRAMMABLE DIVIDER
1/2fDIV
FL
TDA6404 TDA6405 TDA6405A
7-BIT CONTROL REGISTER
POWER-ON RESET FL
15-BIT FREQUENCY REGISTER CHP T2
T1
T0 RSA RSB OS
SCL SDA AS
12 (17) 11 (18) 10 (19)
SCL SDA AS
I2C-BUS TRANSCEIVER FL fREF 1/2fDIV
3-BIT BAND SWITCH REGISTER VHFL VHFH UHF (9) 20 GND
5-LEVEL A/D CONVERTER
GATE
VCC T2, T1, T0
BS
13 (16) ADC
7 (22) PVHFL
8 (21) PVHFH
9 (20) PUHF
MGK813
The pin numbers in parenthesis represent the TDA6405 and TDA6405A.
Fig.1 Block diagram.
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
PINNING PIN SYMBOL TDA6404 UHFIN1 UHFIN2 VHFIN RFGND IFFIL1 IFFIL2 PVHFL PVHFH PUHF AS SDA SCL ADC CP VT XTAL VCC IFOUT1 IFOUT2 GND UHFOSCIB1 UHFOSCOC1 UHFOSCOC2 UHFOSCIB2 VHFOSCIB1 VHFOSCOC1 VHFOSCOC2 VHFOSCIB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TDA6405; TDA6405A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 UHF input 1 UHF input 2 VHF input RF ground IF filter output 1 IF filter output 2
TDA6404; TDA6405; TDA6405A
DESCRIPTION
PNP port output for VHF low band PNP port output for VHF high band PNP port output for UHF band address selection input serial data input/output (I2C-bus) serial clock input (I2C-bus) Analog-to-Digital Converter input/output charge pump output tuning output crystal oscillator input supply voltage IF amplifier output 1 IF amplifier output 2 ground UHF oscillator base input 1 UHF oscillator collector output 1 UHF oscillator collector output 2 UHF oscillator base input 2 VHF oscillator base input 1 VHF oscillator collector output 1 VHF oscillator collector output 2 VHF oscillator base input 2
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TDA6404; TDA6405; TDA6405A
handbook, halfpage
handbook, halfpage
UHFIN1 1 UHFIN2 2 VHFIN 3 RFGND 4 IFFIL1 5 IFFIL2 6 PVHFL 7
28 VHFOSCIB2 27 VHFOSCOC2 26 VHFOSCOC1 25 VHFOSCIB1 24 UHFOSCIB2 23 UHFOSCOC2 22 UHFOSCOC1
VHFOSCIB2 1 VHFOSCOC2 2 VHFOSCOC1 3 VHFOSCIB1 4 UHFOSCIB2 5 UHFOSCOC2 6 UHFOSCOC1 7 UHFOSCIB1 8 GND 9 IFOUT2 10 IFOUT1 11 VCC 12 XTAL 13 VT 14
MGK831
28 UHFIN1 27 UHFIN2 26 VHFIN 25 RFGND 24 IFFIL1 23 IFFIL2
TDA6404
PVHFH 8 PUHF 9 AS 10 SDA 11 SCL 12 ADC 13 CP 14
MGK830
21 UHFOSCIB1 20 GND 19 IFOUT2 18 IFOUT1 17 VCC 16 XTAL 15 VT
TDA6405 22 PVHFL TDA6405A 21 PVHFH
20 PUHF 19 AS 18 SDA 17 SCL 16 ADC 15 CP
Fig.2 Pin configuration for TDA6404.
Fig.3 Pin configuration for TDA6405(A)
FUNCTIONAL DESCRIPTION The devices are controlled via the I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for selecting the read or write mode. Write mode Data bytes can be sent to the devices after the address transmission (first byte) by setting the R/W bit to logic 0. Four data bytes are needed to fully program the devices. The I2C-bus transceiver has an auto-increment facility which permits the programming of the devices within one single transmission (address + 4 data bytes). The devices can also be partially programmed, providing that the first data byte following the address is divider byte 1 (DB1) or control byte (CB). The bits in the data bytes are defined in Tables 1 and 2.
The first bit of the data byte transmitted indicates whether frequency data (first bit = 0) or control and band switch data (first bit = 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional data bytes can be entered without the need to re-address the devices. The frequency register is loaded after the 8th clock pulse of the second divider byte (DB2). The control register is loaded after the 8th clock pulse of the CB. The band switch register is loaded after the 8th clock pulse of the band switch byte (BB).
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Table 1 I2C-bus mode, write data format for the TDA6404 and TDA6405 BITS NAME Address byte Divider byte 1 Divider byte 2 Control byte Band-switch byte Table 2 BYTE MSB ADB DB1 DB2 CB BB 1 0 N7 1 X 1 N14 N6 CHP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 X
TDA6404; TDA6405; TDA6405A
ACK LSB MA1 N10 N2 RSA UHF MA0 N9 N1 RSB VHFH R/W = 0 N8 N0 OS VHFL A A A A A
I2C-bus mode, write data format for the TDA6405A BITS BYTE MSB LSB 1 N14 N6 CHP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 UHF MA1 N10 N2 RSA X MA0 N9 N1 RSB VHFH R/W = 0 N8 N0 OS VHFL A A A A A ADB DB1 DB2 CB BB 1 0 N7 1 X ACK
NAME Address byte Divider byte 1 Divider byte 2 Control byte Band-switch byte
I2C-bus address selection The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 4) in one system by applying a specific voltage on the AS input. The relationship between MA1 and MA0 and the input voltage applied to the AS input is given in Table 4. Table 3 Description of symbols used in Tables 1 and 2 SYMBOL A MA1 and MA0 N14 to N0 CHP acknowledge programmable address bits (see Table 4) programmable divider bits; N = N14 x 214 + N13 x 213 + ... + N1 x 21 + N0 charge pump current bit: CHP = 0; ICP = 60 A CHP = 1; ICP = 280 A (default) T2, T1 and T0 RSA and RSB OS test bits (see Table 5) reference divider ratio select bits (see Table 6) tuning amplifier control bit: OS = 0; normal operation; tuning voltage is `ON' OS = 1; tuning voltage is `OFF' (high-impedance) UHF, VHFH and VHFL PNP ports control bits: bit = 0; buffer n is `OFF' (default) bit = 1; buffer n is `ON' X don't care bit: may be a logic 0 or a logic 1 DESCRIPTION
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Table 4 MA1 0 0 1 1 Table 5 T2 0 0 0 1 1 1 1 Notes 1. This is the default mode at Power-on reset. 2. The ADC input cannot be used when these test modes are active. Table 6 Reference divider ratio select bits RSB 0 1 1 REFERENCE DIVIDER RATIO 640 1024 512 Address selection I2C-bus MA0 0 1 0 1 Test mode T1 0 0 1 1 1 0 0 T0 0 1 X 0 1 0 1 automatic charge pump off automatic charge pump on; note 1 charge pump is `OFF' charge pump is sinking current charge pump is sourcing current fREF is available on pin ADC; note 2
1 2fDIV
TDA6404; TDA6405; TDA6405A
VOLTAGE APPLIED ON AS INPUT 0 to 0.1VCC open or 0.2VCC to 0.3VCC 0.4VCC to 0.6VCC 0.9VCC to 1.0VCC
TEST MODES
is available on pin ADC; note 2
RSA X 0 1 Read mode
FREQUENCY STEP (kHz) 6.25 3.90625 7.8125
Data can be read from the devices by setting the R/W bit to logic 1 (see Tables 7 and 8). After the slave address has been recognized, the devices generate an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH-level of the SCL clock signal. A second data byte can be read from the devices if the processor generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The devices will then release the data line to allow the processor to generate a STOP condition. The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is detected by the devices (end of a read sequence). Control of the loop is made possible with the in-lock flag FL which indicates when the loop is locked (FL = 1).
The ACPS flag is LOW when the automatic charge pump switch mode is `ON' and the loop is locked. In other conditions, ACPS = 1. When ACPS = 0, the charge pump current is forced to the LOW value. A built-in ADC is available on ADC pin. This converter can be used to apply AFC information to the controller from the IF section of the television. The relationship between the bits A2, A1 and A0 is given in Table 9.
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Table 7 Read data format BITS NAME Address byte Status byte Note 1. MSB is transmitted first. Table 8 Description of symbols used in Table 7 DESCRIPTION acknowledge Power-on reset flag (POR = 1 at power-on) in-lock flag (FL = 1 when the loop is locked) automatic charge pump switch flag: ACPS = 0; active ACPS = 1; not active A2, A1 and A0 Table 9 digital outputs of the 5-level ADC (see Table 9) BYTE ADB SB MSB(1) 1 POR 1 FL 0 ACPS 0 1 0 1
TDA6404; TDA6405; TDA6405A
ACK LSB MA1 A2 MA0 A1 R/W = 1 A0 A -
SYMBOL A POR FL ACPS
Analog-to-digital converter levels; note 1 A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 VOLTAGE APPLIED ON ADC INPUT 0.60VCC to 1.00VCC 0.45VCC to 0.60VCC 0.30VCC to 0.45VCC 0.15VCC to 0.30VCC 0 to 0.15VCC
Note 1. Accuracy is 0.03VCC. Power-on reset The power-on detection threshold voltage VPOR is set to VCC = 2 V at room temperature. Below this threshold, the device is reset to the power-on state. At power-on state, the charge pump current is set to 280 A, the tuning voltage output is disabled, the test bits T2, T1 and T0 are set to logic 001 (automatic charge pump switch `ON') and RSB is set to logic 1. PUHF is `OFF', which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the VHF oscillator and the VHF mixer are switched on. PVHFL and PVHFH are `OFF', which means that the VHF tank circuit is working in the VHF I sub-band. The tuning amplifier is switched off until the first transmission. In that case, the tank circuit in VHF I is supplied with the maximum tuning voltage. The oscillator is therefore working at the end of the VHF I sub-band.
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Table 10 Default bits at Power-on reset BITS NAME Address byte Divider byte 1 Divider byte 2 Control byte Band-switch byte BYTE MSB ADB DB1 DB2 CB BB 1 0 X 1 X 1 X X 1 X 0 X X 0 X 0 X X 0 X 0 X X 1 0
TDA6404; TDA6405; TDA6405A
LSB MA1 X X X 0 MA0 X X 1 0 X X X 0 0
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) (note 1). SYMBOL VCC VO(n) IO(n) VO(CP) VO(VT) VI/O(ADC) VI(SCL) VI/O(SDA) IO(SDA) VI(AS) VI(XTAL) IO(n) supply voltage output voltage on pins PVHFL, PVHFH and PUHF output current on pins PVHFL, PVHFH and PUHF charge pump output voltage tuning output voltage ADC input/output voltage serial clock input voltage serial data input/output voltage data output current address selection input voltage crystal oscillator input voltage output current of each pin to ground: for TDA6404, pins 1 to 6 and 17 to 28 for TDA6405 and TDA6405A, pins 1 to 12 and 23 to 28 tsc(max) Tstg Tamb Tj Note 1. Maximum ratings can not be exceeded, not even momentarily without causing irreversible IC damage. Maximum ratings can not be accumulated. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air TYPICAL 85 UNIT K/W maximum short-circuit time (all pins to VCC and all pins to GND, RFGND) IC storage temperature operating ambient temperature junction temperature - - - -40 -20 - -10 -10 10 +150 +85 150 mA mA s C C C PARAMETER MIN. -0.3 -0.3 -1 -0.3 -0.3 -0.3 -0.3 -0.3 -1 -0.3 -0.3 MAX. +6 +6 +30 +6 +35 +6 +6 +6 +10 +6 +6 UNIT V V mA V V V V V mA V V
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
CHARACTERISTICS SYMBOL PARAMETER CONDITIONS
TDA6404; TDA6405; TDA6405A
MIN.
TYP.
MAX.
UNIT
Supply (Tamb = 25 C) VCC ICC supply voltage supply current at VCC = 5 V all PNP ports are `OFF' one PNP port is `ON', sourcing 25 mA 4.5 - - 5 78 110 5.5 86 121 V mA mA
PLL Synthesizer part (VCC = 4.5 to 5.5 V; Tamb = -20 to +85 C; unless otherwise specified) FUNCTIONAL RANGE VPOR D/D fXTAL ZXTAL PNP PORTS IL(off) VO(sat) ADC INPUT VI IIH IIL VIL VIH IIH IIL VIL VIH IIH IIL fSCL IL VO ADC input voltage HIGH-level input current LOW-level input current see Table 9 VADC = VCC VADC = 0 0 - -10 0 3 VAS = 5.5 V VAS = 0 - -10 0 3.0 Vbus = 5.5 V; VCC = 0 Vbus = 5.5 V; VCC = 5.5 V LOW-level input current serial clock frequency Vbus = 1.5 V; VCC = 0 Vbus = 0; VCC = 5.5 V SDA OUTPUT leakage current output voltage VSDA = 5.5 V ISDA = 3 mA (sink current) - - - - 10 0.4 A V - - - -10 - - - - - - - - - - - - - - 100 VCC 10 - 1.5 5.5 10 - 1.5 5.5 10 10 10 - 150 V A A V V A A V V A A A A kHz leakage current output saturation voltage VCC = 5.5 V; VPNPn = 0 one PNP port is `ON', sourcing 25 mA; VPNPn(sat) = VCC - VPNPn -10 - - 0.25 - 0.4 A V Power-on reset voltage divider ratio input impedance below this supply voltage Power-on reset becomes active; see Table 10 15-bit frequency word fXTAL = 4 MHz 1.5 256 3.2 600 2.0 - 4 1200 - 32767 4.48 - MHz V
crystal oscillator frequency RXTAL = 25 to 150
ADDRESS SELECTION INPUT (AS) LOW-level input voltage HIGH-level input voltage HIGH-level input current LOW-level input current
SCL AND SDA INPUTS LOW-level input voltage HIGH-level input voltage HIGH-level input current
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
SYMBOL IIH IIL VO IL(off) IL(off) VO PARAMETER CONDITIONS - - -
TDA6404; TDA6405; TDA6405A
MIN. TYP. MAX. - - - +15 UNIT A A V nA A V
CHARGE PUMP OUTPUT (CP) HIGH-level input current LOW-level input current output voltage off-state leakage current CHP = 1 CHP = 0 PLL is locked; Tamb = 25 C T2 = 0; T1 = 1 280 60 1.95 -0.5 - -
-15 - 0.2
TUNING VOLTAGE OUTPUT (VT) off-state leakage current output voltage when the loop is closed OS = 1; tuning supply = 33 V OS = 0; T2 = 0; T1 = 0; T0 = 1; RL = 27 k; tuning supply = 33 V 10 32.7
Mixer/oscillator part (VCC = 5 V; Tamb = 25 C; unless otherwise specified); measured in Fig.11 IF AMPLIFIER S22 Rs Ls output reflection coefficient magnitude at 36.15 MHz; Zo = 50 phase at 36.15 MHz; Zo = 50 real part of Zo = Rs + jLs imaginary part of Zo = Rs + jLs RF input frequency noise figure Rs at 36.15 MHz Ls at 36.15 MHz - - - - -12.5 1.41 81 9.5 - - - - dB deg nH
VHF MIXER (INCLUDING IF AMPLIFIER) fi(RF) F picture carrier frequency fRF = 50 MHz; see Figs 8 and 9 fRF = 150 MHz; see Figs 8 and 9 fRF = 300 MHz; gos optimum source conductance for noise figure input conductance input capacitance output voltage causing 1% cross modulation in channel fRF = 50 MHz fRF = 150 MHz fRF = 300 MHz fRF = 45.25 MHz fRF = 399.25 MHz Ci Vo fRF = 45.25 to 399.25 MHz fRF = 45.25 MHz; see Fig.6 fRF = 399.25 MHz; see Fig.6 45.25 - - - - - - - - - 116 116 - 24.5 24.5 - 7 8 9 0.7 0.9 1.5 0.25 0.5 2 119 119 88 27 27 - 100 200 399.25 MHz 9 10 11 - - - - - - - - - 29.5 29.5 dB dB dB mS mS mS mS mS pF dBV dBV dBV dB dB
gi
Vi GV
input voltage causing fRF = 399.25 MHz; note 1 pulling in channel (750 Hz) voltage gain fRF = 45.25 MHz; see Fig.4 fRF = 399.25 MHz; see Fig.4
VHF OSCILLATOR fosc fosc(V) oscillator frequency oscillator frequency shift with supply voltage 84.15 VCC = 5%; worst case in the frequency - range; note 2 VCC = 10%; worst case in the frequency range; note 2 - 438.15 MHz 200 - kHz kHz
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
SYMBOL fosc(T) fosc(t) osc RSC(p-p) PARAMETER oscillator frequency drift with temperature oscillator frequency drift with time phase noise, carrier to noise sideband ripple susceptibility of VCC (peak-to-peak value) CONDITIONS T = 25 C with compensation; worst case in the frequency range; note 3 with compensation; worst case in the frequency range; note 4 100 kHz frequency offset; worst case in the frequency range - - -
TDA6404; TDA6405; TDA6405A
MIN. TYP. 1300 600 106 40 MAX. 2000 900 - - UNIT kHz kHz dBc/Hz mV
VCC = 5 V; worst case in the frequency 15 range; ripple frequency 500 kHz; note 5
UHF MIXER (INCLUDING IF AMPLIFIER) fi(RF) F RF input frequency noise figure picture carrier frequency fRF = 407.25 MHz; not corrected for image; see Fig.10 fRF = 855.25 MHz; not corrected for image; see Fig.10 Rs Ls Vo real part of Zi = Rs + jLs imaginary part of Zi = Rs + jLs output voltage causing 1% cross modulation in channel fRF = 407.25 MHz fRF = 855.25 MHz fRF = 407.25 MHz fRF = 855.25 MHz fRF = 407.25 MHz; see Fig.7 fRF = 855.25 MHz; see Fig.7 407.25 - - - - - - - 116 114 - 35 35 8 9 30 38 9 6 119 117 78 38 38 855.25 MHz 10 11 - - - - - - - 41 41 dB dB nH nH dBV dBV dBV dB dB
Vi GV
input voltage causing fRF = 855.25 MHz; note 1 pulling in channel (750 Hz) voltage gain fRF = 407.25 MHz; see Fig.5 fRF = 855.25 MHz; see Fig.5
UHF OSCILLATOR fosc fosc(V) oscillator frequency oscillator frequency shift with supply voltage 446.15 - VCC = 5%; worst case in the frequency - range; note 2 VCC = 10%; worst case in the frequency range; note 2 fosc(T) fosc(t) osc RSC(p-p) oscillator frequency drift with temperature oscillator frequency drift with time phase noise, carrier to noise sideband ripple susceptibility of VCC (peak-to-peak value) T = 25 C; with compensation; worst case in the frequency range; note 3 with compensation; worst case in the frequency range; note 4 100 kHz frequency offset; worst case in the frequency range - - - - 30 80 600 200 106 20 894.15 MHz 80 - 1000 400 - - kHz kHz kHz kHz dBc/Hz mV
VCC = 5 V; worst case in the frequency 15 range; ripple frequency 500 kHz; note 5
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
SYMBOL PARAMETER CONDITIONS -
TDA6404; TDA6405; TDA6405A
MIN. TYP. MAX. - UNIT
REJECTION AT THE IF AMPLIFIER OUTPUT INTDIF level of divider interferences in the IF signal crystal oscillator interferences rejection note 6 20 dBV
INTRXTAL
note 7 note 8 note 9 note 10
60 50 60 66
- - - -
- - - -
dBc dBc dBc dBc
INTRFREF reference frequency rejection INTCHX INTS02 Notes channel x beat S02 beat
1. This is the level of the RF signal (100% amplitude modulated with 11.89 kHz) that causes a 750 Hz frequency deviation on the oscillator signal; it produces sidebands 30 dB below the level of the oscillator signal. 2. The frequency shift is defined as the change of the oscillator frequency when the supply voltage varies from VCC = 5 to 4.75 V (4.5 V) or from VCC = 5 to 5.25 V (5.5 V). The oscillator is free-running during this measurement. 3. The frequency drift is defined as the change of the oscillator frequency when the ambient temperature varies from Tamb = 25 to 0 C or from Tamb = 25 to 50 C. The oscillator is free-running during this measurement. 4. The switching on drift is defined as the change of the oscillator frequency between 5 seconds and 15 minutes after switching on. The oscillator is free-running during this measurement. 5. The ripple susceptibility is measured for a 500 kHz ripple at the IF amplifier output using the measurement circuit; the level of the ripple signal is increased until a difference of 53.5 dB between the IF carrier set at 100 dBV and the sideband components is reached. 6. This is the level of divider interferences close to the IF frequency. For example: Ch S1: fosc = 144.15 MHz and 14fosc = 36.0375 MHz. Ch S2: fosc = 151.15 MHz and 14fosc = 37.7875 MHz. Ch S14: fosc = 291.15 MHz and 18fosc = 36.39375 MHz. The VHF RF input must be left open (i.e. not connected to any load or cable). The UHF RF inputs are connected to a hybrid. 7. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection should be >60 dB for an IF output signal of 100 dBV. 8. The reference frequency rejection is the level of reference frequency sidebands related to the sound subcarrier. The rejection should be >50 dB for an IF output signal of 100 dBV, fREF = 7.8125 kHz. 9. Channel x beat: picture carrier frequency (69.25 MHz) and sound carrier frequency (74.75 MHz) both at 80 dBV, fosc at 108.15 MHz. The rejection of the interfering product RF picture carrier frequency + RF sound carrier frequency - fosc at 35.85 MHz should be >60 dB. 10. Channel S02: picture carrier frequency is 76.25 MHz at 80 dBV, fosc = 115.15 MHz. The rejection of fosc - 2 x fIF = 37.35 MHz should be >66 dB.
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TEST AND APPLICATION INFORMATION
TDA6404; TDA6405; TDA6405A
handbook, full pagewidth
50
signal source VHFIN IFOUT1
(1)
T
(2)
spectrum analyzer V'meas 50
e
Vmeas V
50
Vi
D.U.T.
IFOUT2
Vo
N1 C
N2
RMS voltmeter
MGK828
(1) N1 is 2 x 5 turns (2) N2 is 2 turns Zi >> 50 Vi = 2 x Vmeas; Vi = 80 dBV N1 Vo = V'meas + 16 dB (transformer ratio ------- = 5 and transformer loss) N2 Vo Gv = 20 log ----Vi
Fig.4 Voltage gain (Gv) measurement in the VHF band.
handbook, full pagewidth
50
signal source A C UHFIN1 IFOUT1
(1)
T
(2)
spectrum analyzer V'meas 50
e
Vmeas V
50
Vi
HYBRID
D.U.T.
UHFIN2 IFOUT2
Vo
N1 C
N2
B RMS 50 voltmeter
D
MGK829
(1) N1 is 2 x 5 turns (2) N2 is 2 turns Vi = Vmeas; Vi = 70 dBV N1 Vo = V'meas + 16 dB (transformer ratio ------- = 5 and transformer loss) N2 Vo Gv = 20 log ----- + 1 dB (1 dB = correction for hybrid loss) Vi
Fig.5 Voltage gain (Gv) measurement in the UHF band.
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TDA6404; TDA6405; TDA6405A
handbook, full pagewidth
Vmeas
V
50 RMS voltmeter 18 dB attenuator 38.9 MHz
(2)
unwanted signal 50 source A eu AM = 30% HYBRID 50 ew wanted signal source Vi C
FILTER T
(1)
VHFIN IFOUT1 Vo N1 C
modulation analyzer 50
D.U.T.
N2
V V'meas
B
D 50
IFOUT2 RMS voltmeter
MGL275
(1) N1 is 2 x 5 turns (2) N2 is 2 turns N1 Zi >> 50 Vi = 2 x Vmeas; V'meas = Vo - 16 dB (transformer ratio ------- = 5 and transformer loss) N2 Wanted input signal Vi = 80 dBV at wanted fRF = 45.25 MHz (399.25 MHz). Measured level of the unwanted output signal Vou causing 0,3% AM modulation in the wanted output signal; unwanted fRF = 50.75 MHz (404.75 MHz); Vou = V'meas + 16 dB.
Fig.6 Cross modulation measurement in the VHF band.
handbook, full pagewidth
Vmeas
V
50 RMS voltmeter T
(1) (2)
unwanted signal 50 source A eu AM = 30% HYBRID 50 ew wanted signal source Vi C
FILTER 18 dB attenuator 38.9 MHz V modulation analyzer 50 UHFIN1 IFOUT1 Vo N1 C
A
C
N2
HYBRID
D.U.T.
B
D 50 50
B
D
UHFIN2 IFOUT2 RMS voltmeter
MGL276
(1) N1 is 2 x 5 turns (2) N2 is 2 turns N1 Vi = Vmeas; V'meas = Vo - 16 dB (transformer ratio ------- = 5 and transformer loss) N2 Wanted input signal Vi = 70 dBV at fRF = 407.25 MHz (855.25 MHz). Measured level of the unwanted output signal Vou causing 0,3% AM modulation in the wanted output signal; unwanted fRF = 412.75 MHz (860.75 MHz); Vou = V'meas + 16 dB.
Fig.7 Cross modulation measurement in the UHF band.
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TDA6404; TDA6405; TDA6405A
handbook, full pagewidth
I1 C1
PCB BNC C3
I3
PCB
BNC
L1
C2
plug RIM-RIM
I2
plug RIM-RIM
C4
(a)
(b)
MBE286 - 1
(a) For fRF = 50 MHz: VHF mixer frequency response measured = 57 MHz; loss = 0 dB. Image suppression = 16 dB. C1 = 9 pF; C2 = 15 pF. L1 = 7 turns (O 5.5 mm; wire O = 0.5 mm). I1 = semi rigid cable (RIM): 5 cm long. (semi rigid cable (RIM); 33 dB/100 m; 50 ; 96 pF/m).
(b) For fRF = 150 MHz: VHF mixer frequency response measured = 150.3 MHz; loss = 1.3 dB. Image suppression = 13 dB. C3 = 5 pF; C4 = 25 pF. I2 = semi rigid cable (RIM): 30 cm long. I3 = semi rigid cable (RIM): 5 cm long (semi rigid cable (RIM); 33 dB/100 m; 50 ; 96 pF/m).
Fig.8 Input circuit for optimum noise figure in the VHF band.
handbook, full pagewidth
NOISE SOURCE
BNC
RIM
VHFIN IFOUT1
T
NOISE FIGURE METER
INPUT CIRCUIT
D.U.T.
IFOUT2
C
MGL277
F = Fmeas - loss (of input circuit) (dB).
Fig.9 Noise figure (F) measurement in the VHF band.
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TDA6404; TDA6405; TDA6405A
handbook, full pagewidth
NOISE SOURCE
A
C
UHFIN1 IFOUT1
T
NOISE FIGURE METER
HYBRID
D.U.T.
C
B 50
D
UHFIN2 IFOUT2
MGL278
Loss (in hybrid) = 1 dB. F = Fmeas - loss (in hybrid).
Fig.10 Noise figure (F) measurement in the UHF band.
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TDA6404; TDA6405; TDA6405A
handbook, full pagewidth
P1 UHF1 1 nF P2 UHF2 1 nF P3 VHF 1 nF L3 TOKO 7 km L value/C value 6 7 1 15 pF 2 4 8 D5 VHFL LED-3R D6 VHFH LED-3Y D7 UHF LED-3G R8 330 R10 330 R11 330 J1 J2 J3 J4 J7 AS VHFH VHFL UHF PLL 10 (19) (10) 19 IFOUT2 C19 1 nF R12 330 VCC VCC J5 +VCC TR1 BC847B P5 R13 330 ADC SCL SDA 11 (18) (11) 18 IFOUT1 C20 1 nF 12 (17) (12) 17 VCC L9 80 nH L8 80 nH C22 10 nF X1 13 (16) (13) 16 XTAL C23 VCC 4 MHz 18 pF CP 14 (15) C25 100 nF 10 F (16 V) R19 330 P7 1 SCL GND 2 3 SDA +5 V 4 5 6 J6 (14) 15 VT R15 33 k R17 1.2 k C27 10 F C28 (16 V) R22 50 P9 Vripple C26 2.2 nF P10 fREF 1 AGND 2 3 4 P8 R16 22 k P6 R14 22 k C24 10 nF C21 18 pF 1 2 3 L7 8 4 7 6 P4 IF OUT 3 C11 C13 IFFIL2 15 pF PVHFL UHFOSCOC1 RFGND 4 (25) (4) 25 VHFOSCIB1 C6 VHFIN 3 (26) (3) 26 C3 UHFIN2 2 (27) (2) 27 VHFOSCOC2 C1 C2 150 pF D1 C4 D2 BB152 R21 R2 C9 100 pF L2 30 nH C5 4.7 nF L4 80 nH C10 4.7 nF R7 22 k D4 BB149 R6 22 k C15 47 pF C18 10 pF R9 4.7 k L5 16 nH L6 30 nH R1 1.5 k R3 22 k D3 BA792 R4 1.5 k R5 2.7 k VHFL VHFH C30 4.7 nF BB149 L1 1 H
UHFIN1
1 (28)
(1) 28
VHFOSCIB2
2.2 pF VHFOSCOC1 C7 2.2 pF C8 2.2 pF IFFIL1 5 (24) (5) 24 UHFOSCIB2 C12 1 pF 6 (23) (6) 23 UHFOSCOC2 C14 1 pF C16 1 pF C17 1 pF PUHF 9 (20) (9) 20 GND 7 (22) TDA6404 (7) 22 (TDA6405) (TDA6405A) PVHFH UHFOSCIB1 (8) 21 8 (21) 22 k 22 k
for test purpose only
for test purpose only
R18 1 k C29 10 nF R20 68 k for test purpose only TR2 BC847B
+VCC
+VCC +5 V
MGK812
+33 V
The pin numbers in parenthesis represent the TDA6405 and TDA6405A.
Fig.11 Measurement circuit.
1999 Jan 13
19
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Component values for measurement circuit Table 11 Capacitors (all SMD and NP0 unless otherwise specified) COMPONENT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 1 nF 150 pF 1 nF 2.2 pF (N750) 4.7 nF 1 nF 2.2 pF (N750) 2.2 pF (N750) 100 pF (N750) 4.7 nF 15 pF 1 pF (N750) 15 pF 1 pF (N750) 47 pF 1 pF (N750) 1 pF (N750) 10 pF (N750) 1 nF 1 nF 18 pF 10 nF 18 pF 10 nF 100 nF 2.2 nF 10 F (16 V; electrolytic) 10 F (16 V; electrolytic) 10 nF 4.7 nF VALUE R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22
TDA6404; TDA6405; TDA6405A
Table 12 Resistors (all SMD) COMPONENT 1.5 k 22 k 22 k 1.5 k 2.7 k 22 k 22 k 330 4.7 k 330 330 330 330 22 k 33 k 22 k 1.2 k 1 k 330 68 k 22 k 50 VALUE
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
Table 13 Diodes and ICs COMPONENT D1 D2 D3 D4 D5 D6 D7 IC BB149 BB152 BA792 BB149 LED-3R LED-3Y LED-3G TDA6404; TDA6405; TDA6405A X1 Table 17 Transistors VALUE 1 H (inductor) 30 nH 80 nH 16 nH 30 nH 80 nH 80 nH TR1 TR2 COMPONENT Table 16 Crystal COMPONENT L7 VALUE L3 Table 15 Transformer COMPONENT
TDA6404; TDA6405; TDA6405A
VALUE 23 turns (TOKO, wire 0.07 mm) N1 = 2 x 5 turns N2 = 2 turns (TOKO, wire 0.09 mm)
VALUE 4 MHz
Table 14 Coils COMPONENT L1 L2 L4 L5 L6 L8 L9
VALUE BC847B BC847B
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
INTERNAL PIN CONFIGURATION PIN SYMBOL TDA6404 UHFIN1 UHFIN2 1 2 TDA6405: TDA6405A 28 27
1 (28) 2 (27)
MGE704
TDA6404; TDA6405; TDA6405A
CONFIGURATION(1)
AVERAGE DC VOLTAGE (V) VHF note 2 note 2 1.0 1.0 UHF
VHFIN
3
26
3 (26)
1.9
note 2
MGE705
RFGND
4
25
4 (25)
MGE706
0.0
0.0
IFFIL1 IFFIL2
5 6
24 23
(24) 5
6 (23)
3.4 3.4
3.4 3.4
MGD617
PVHFL PVHFH PUHF
7 8 9
22 21
7 8 (21)
0.0 or (VCC - VCE) (VCC - VCE) or 0.0 0.0
0.0 0.0 (VCC - VCE)
20
(22)
9 (20)
MGK814
1999 Jan 13
22
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
PIN SYMBOL TDA6404 AS 10 TDA6405: TDA6405A 19 CONFIGURATION(1)
TDA6404; TDA6405; TDA6405A
AVERAGE DC VOLTAGE (V) VHF VAS VAS UHF
10 (19)
MGK815
SDA
11
18
note 2
note 2
11 (18)
MGK816
SCL
12
17
note 2
note 2
12 (17)
MGK817
ADC
13
16
1.9
1.9
13 (16)
MGK818
CP
14
15
1.9
1.9
14 (15)
MGK819
1999 Jan 13
23
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
PIN SYMBOL TDA6404 VT 15 TDA6405: TDA6405A 14
15 (14)
TDA6404; TDA6405; TDA6405A
AVERAGE DC VOLTAGE (V) VHF VVT VVT UHF
CONFIGURATION(1)
MGK820
XTAL
16
13
3.0
3.0
16 (13)
MGK821
VCC IFOUT1 IFOUT2
17 18 19
12 11 10
supply voltage
5.0 2.2 2.2
5.0 2.2 2.2
18 (11)
19 (10)
MGK822
GND
20
9
20 (9)
MGK823
0.0
0.0
UHFOSCIB1 UHFOSCOC1 UHFOSCOC2 UHFOSCIB2
21 22 23 24
8 7 6 5
21 (8) 24 (5) (6) 23 (7) 22
note 2 note 2 note 2 note 2
1.9 2.5 2.5 1.9
MGK824
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
PIN SYMBOL TDA6404 VHFOSCIB1 VHFOSCOC1 VHFOSCOC2 VHFOSCIB2 25 26 27 28 TDA6405: TDA6405A 4 3 2 1
25 (4) 28 (1) (2) 27 (3) 26
TDA6404; TDA6405; TDA6405A
AVERAGE DC VOLTAGE (V) VHF 2.0 2.7 2.7 2.0 UHF note 2 note 2 note 2 note 2
CONFIGURATION(1)
MGK825
Notes 1. The pin numbers in parenthesis represent the TDA6405 and TDA6405A. 2. Not applicable.
1999 Jan 13
25
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
TDA6404; TDA6405; TDA6405A
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
ISSUE DATE 93-09-08 95-02-04
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA6404; TDA6405; TDA6405A
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jan 13
27
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
TDA6404; TDA6405; TDA6405A
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. REFLOW(1)
1999 Jan 13
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Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA6404; TDA6405; TDA6405A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jan 13
29
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
NOTES
TDA6404; TDA6405; TDA6405A
1999 Jan 13
30
Philips Semiconductors
Product specification
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
NOTES
TDA6404; TDA6405; TDA6405A
1999 Jan 13
31
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
SCA61
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Printed in The Netherlands
545004/750/02/pp32
Date of release: 1999 Jan 13
Document order number:
9397 750 04901
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